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(dashed_line_gap_ratio 3.000000) (svgprecision 6) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15.000000) (dxfpolygonmode true) (dxfimperialunits false) (dxfusepcbnewfont true) (psnegative false) (psa4output false) (plotreference false) (plotvalue false) (plotinvisibletext false) (sketchpadsonfab false) (subtractmaskfromsilk false) (outputformat 3) (mirror false) (drillshape 2) (scaleselection 1) (outputdirectory "Plots") ) ) (net 0 "") (net 1 "GND") (net 2 "+3V3") (net 3 "VA_+") (net 4 "VLNA1_+") (net 5 "VLNA2_+") (net 6 "Net-(C1-Pad2)") (net 7 "SWDIO") (net 8 "nRESET") (net 9 "SWCLK") (net 10 "Net-(U2-VI)") (net 11 "Net-(U8-XIN)") (net 12 "+1V1") (net 13 "Net-(C14-Pad1)") (net 14 "SCL") (net 15 "SDA") (net 16 "Net-(C24-Pad1)") (net 17 "Net-(C24-Pad2)") (net 18 "Net-(C26-Pad1)") (net 19 "Net-(C29-Pad1)") (net 20 "Net-(C26-Pad2)") (net 21 "TXD") (net 22 "RXD") (net 23 "VLNA1_-") (net 24 "VLNA2_-") (net 25 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